Senior Design Verification Engineer - San Diego, CA

Only for registered members San Diego, CA, United States

1 month ago

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Job summary

We are seeking a Senior ASIC Design Verification Engineer to verify high-speed mixed-signal IPs used in cutting-edge products for 5G,

Responsibilities

  • Develop and execute pre-silicon and post-silicon verification test plans based on design specifications and industry standards.
  • Architect and implement advanced verification environments using SystemVerilog and UVM.
  • Create and maintain UVM testbenches test sequences scoreboards monitors Write debug SystemVerilog Assertions SVA Develop functional code coverage models drive coverage closure Perform gate-level simulations low-power verification formal verification as required Collaborate closely with digital design analog design modeling subsystem SoC integration teams Support PHY-level verification subsystem integration SoC-level validationdebug Contribute or develop Verification IP VIP for SerDes controller PHY strong plus

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