Senior FPGA Electrical Engineer - BWI Airport, United States - Parallel Partners

Description

Senior FPGA Electrical Engineer, Linthicum Heights, MD

We are looking for multiple Senior FPGA Electrical Engineer candidates at multiple levels for this position.
Candidates must be US Citizens and cannot have Dual Citizenships.
All candidates must be fully vaccinated with an FDA authorized and/or approved COVID-19 vaccine as a condition of employment. Requests for reasonable accommodations for medical, religious, or other reasons will be considered in accordance with applicable law.
These positions are 100% Onsite.


Responsibilities:

• Participate in all phases of FPGA design flow, from concept to mass production.
• Develop highlevel design requirements and blocklevel microarchitectures, partition design within ASIC/FPGA, create specification documents.
• Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer, error correction, etc.).
• Optimize designs for area, speed, and power to meet system requirements; analyze architectural tradeoffs.
• Develop test benches and test cases for blocklevel functional verification, emphasizing bitmatching and selfchecking.
• Verify DSP blocks against fixedpoint MATLAB model, work in collaboration with systems engineers.
• Participate in SoC and FPGA integration activities.
• Prototype designs on FPGA, focusing on closely emulating the final product functionality.
• Perform lint checking, CDC checking, logic equivalence checking, and other EDA toolbased checks.
• Work with backend/implementation teams to address synthesis, timing, layout, and DFT issues for ASICs.
• Bringup and validate ASICs and FPGAs in the lab, utilize various lab equipment.
• Collaborate with software engineers in developing production software for your designs.

Minimum Qualifications:

• 8+ years of experience designing/testing with FPGAs (Xilinx, Altera, etc.).
• 8+ years of experience with SystemVerilog, Verilog, or VHDL RTL design.
• 3+ years of experience leading a team of Engineers.
• Expertise in any industry standard testing frameworks (UVM, UVVM, OSVM, etc.).
• Experience in scripting and programming languages in two or more of the following: MATLAB, Python, C/C++, Tcl, Makefiles, Bash.
• Ability to guide Engineers with diverse skill sets towards deliverable goals.

Preferred Qualifications:

• Some experience in designing DSP or digital communication system datapath blocks (e.g., filters, transforms, PHY blocks, loops, FEC, etc.).
• Experience in Xilinx advanced FPGAs, eval boards, and knowledge of FPGA design flow.
• Knowledge of different digital modulation techniques (e.g., PSK, QAM, OFDMA, etc.).
• Knowledge of wireless communications systems and standards (e.g. ,LTE, Wi-Fi, Bluetooth, etc.).
• Knowledge of industry standard interfaces, protocols, and architectures: PCIe, Ethernet, AMBA, DDR, etc.
• Experience in developing automated, selfchecking test benches.
• Knowledge or understanding of UVM verification framework.
• Experience in EDA tools such as simulators (e.g., Questa), lint checkers (e.g., Spyglass) synthesis (e.g., Synopsys Synplify),
• FPGA tools (e.g., Vivado).
• Experience in synthesis and static timing analysis, knowledge of timing closure techniques for highspeed designs
• Experience in ASIC/FPGA/SoC systemlevel/toplevel integration.
• Familiarity with design for testability (DFT) and high reliability ASIC design and implementations.

Keywords:
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