Staff Digital ASIC Circuit Design Engineer - BWI Airport, United States - Northrop Grumman

Description

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come.

Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon.

We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way.

Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work - and we have an insatiable drive to do what others think is impossible.

Our employees are not only part of history, they're making history.

The Northrop Grumman Mission Systems (NGMS) Advanced Processing Solutions Business pushes the boundaries of innovation, redefines the leading edge of exotic new technologies, and drives advances in the sciences.

One of our most challenging new fields is Transformational Computing, which combines the unique properties of superconductivity and quantum mechanics to develop radical new energy-efficient computing systems.

Our team is chartered with providing the skills to transform computing beyond Moore's Law, advancing development of computer architectures, processing/memory subsystems, and large scale high performance computing systems.

You'll work in a fast-paced team environment alongside a broad array of scientists and engineers to make these processing solutions a reality and deliver remarkable new advantages to the warfighter.

We are seeking a front-end ASIC design engineer for design and verification of full-custom digital and mixed signal Superconducting Circuits.

Must be proficient in Verilog, System Verilog or VHDL RTL coding, writing functional test benches and have a thorough understanding of synchronous digital design concepts.

Must be able to create a functional verification plan based on requirements of the circuit. Able to generate manufacturing test vectors and manufacturing test plan. Must be knowledgeable in synthesis, SDC constraints, formal verification, and static timing. Knowledge of scan insertion and ATPG is a plus. Able to interface with place and route engineers for floor planning and clocktree constraints and timing closure. Automated place and route and physical verification knowledge is a plus. Must have strong written and oral communication skills.


Responsibilities:
Circuit behavioral coding in Verilog, System Verilog or VHDL RTL.

Circuit synthesis, formal verification, and static timing using state of the art digital ASIC design tools.

Developing verification plans based on requirements of the circuit and creating circuit functional test benches in RTL.

Generating manufacturing test vectors and manufacturing circuit test plan

Help to develop automated procedures to streamline digital design procedures.

This position requires onsite work at our Advanced Technology Lab in Linthicum, MD.

Basic Qualifications for Staff Digital ASIC

Circuit Design Engineer Level:

Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 14 years of relevant experience (12 years with STEM Master's and 9 years with Ph.

D.).

Experience with full product life cycle (requirements, design, implementation, test) of ASIC design.

Working knowledge of the front-end ASIC design flow from RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion).

Proficiency with current ASIC design tools for all phases described below: Simulation - Mentor ModelSim, Cadence Excelium, Incisive or Synopsys VCS - Synthesis - Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler - Static Timing - Synopsys Primetime or Cadence Tempus.

U.S. Citizenship with the ability to obtain and maintain US Security Clearance.


Preferred Qualifications:
Advanced Degree - either MS or PhD.

Current security clearance or eligibility.

Experience with chip level integration and ASIC chip lead - Strong design automation skills.

Experience in CAD design network, tool configuration, and data management.

Familiarity with custom layout in Virtuoso, and physical verification (LVS/DRC) in Assura or Calibre Familiarity with revision control and EDA standard formats used in cell/library development and modeling - Liberty (timing model), SDC (Synopsys Design Constraints).

Active DoD Top Secret Clearance.


Salary Range:
$173,200 - $259,800

The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions.

Employees may be eligible for a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives.

In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.

The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.

Northrop Grumman is committed to hiring and retaining a diverse workforce.

We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class.

For our complete EEO/AA and Pay Transparency statement, please visit . U.S. Citizenship is required for most positions.

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