Muhammed Ceylan Morgul

• Specialized in ASIC/SoC, FPGA, and VLSI design with extensive cross-domain expertise in AI hardware and memory systems, emerging computing, processing-in-memory, reliability, and nano-crossbar arrays, contributing to multiple large-scale, multi-institutional research projects.
• Proficient in guiding the entire silicon design flow (design, verification, layout / physical design, RTL to GDSII generation) using Open-source, Cadence, and Synopsys tools, as well as FPGA implementations.
• Expertise in semiconductor reliability analysis focused on Flash memory aligned with JEDEC standards. 
• Published over 15 peer-reviewed research papers recognized at top-tier venues (IEEE TNANO, IEEE MICRO, IEEE ISVLSI, DATE) and served as lead researcher in multi-institutional collaborations, including as Principal Investigator (PI).
• Enjoys sourdough baking, preparing fermented foods, hosting, Mediterranean music and foods, and photography.

Founding ASIC / FPGA Engineer and Advisor, Stealth Startup, Feb 2025 - Jul 2025

Graduate Research Assistant, University of Virginia, Jan 2019 - May 2025

ASIC, FPGA, and VLSI Design and Verification:
• Co-instructor of Advanced Digital Design and taught Cadence, Synopsys, and open-source EDA tools using advanced process nodes (FinFET 7nm, 14nm, 28nm, 90 nm, etc.)
• Provided more than 10 class tutorials, automation scripts, and debugging assistance for students and peers
• Led over 75 student projects to successful implementations (5 tapeouts) in ASIC/SoC, FPGA, VLSI Design, such as involving standard cells, I2C, SPI, DSP, RISC-V, AMD Xilinx Zynq processor, Quartus Nios II processor, AXI, APB, Wishbone, Neural Networks, etc.
AI Hardware:
• Guided more than 20 student projects in AI Hardware covering BrainChip Akida, Google Coral, Syntiant TinyML, OpenMV, Hailo-8, NVIDIA Jetson Nano, Intel Movidius Myriad X, etc.
• Mentored the ’TIDENet’ project, a finalist in the IEEE SSCS PICO Design Contest, by providing expertise in neural network implementation and SoC generation workflows, and by generating memory blocks 
PiM-CLASH: Cross-Layer Accelerated Self-Healing for PiM:
• Developed a model and SSD-simulator (in C++) for Proactive Recovery and Page Isolation, extending NAND Flash endurance by 9× and increasing sustainability by 3× with C++, Python, and MATLAB
• Created schematic capture of Approximate Binary Neural Network with SkyWater 130 nm open-PDK SONOS flash device in Xschem to run pre-fabrication simulation
• Set up ARM-based STM embedded system reliability testing environments for Flash memory, aligning with JEDEC standards
• Contributed to a $29.7 million national research center (10 U.S. universities) of Semiconductor Research Company by publishing over 7 peer-reviewed papers, and developing models and tools to enhance flash memory reliability for emerging processing-in-memory applications

University of Virginia, PhD, Electrical Engineering, 2019 - 2025

Istanbul Technical University, Master's, Electronics Engineering, 2014 - 2017