- Contribute to SWaP, radiation hardened, and space-rated device projects.
- Create a tailored verification strategy for specific designs.
- Utilize SystemVerilog and Universal Verification Methodology (UVM).
- Define requirements, develop test cases, construct test benches, compile reports, and document verification outcomes.
- Collaborate with a dedicated design team to document and address design flaws.
- Provide support across all phases of ASIC and FPGA development, covering architecture, design, and analysis.
- Participate in and deliver technical presentations.
- More than 11 years of experience in:
- Implementing UVM verification methodology.
- Creating test cases.
- Building test benches for FPGA / ASIC designs to deliver varied stimuli.
- Recognizing and applying required test exclusions.
- Producing coverage reports (code and functional).
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UVM Verification Engineer - Littleton, United States - GeoLogics Corporation
Description
FPGA Engineer - UVM Verification
Clearance Required - Active DOD Secret Clearance
Location - Littleton, CO (Remote Opportunity)
Rate: $70 to 89 an hour (depending on qualifications)
Have experience with UVM Verifications? Have you adapted processes to align with UVM methodology?
Our team is looking for a FPGA Engineer to join our Colorado-based team. This position offers a remote work option for suitable candidates.
Key Responsibilities:
Requirements:
Mary Maves
Intel & Space Sr Recruiter
*Rates listed are an estimate and not a fixed salary/rate. Actual rate offered will depend on various factors such as education, experience, interview performance, and skill level.
GeoLogics is dedicated to employing a diverse and skilled workforce and is an Equal Opportunity/Affirmative Action Employer. EOE/Disability/Veteran
